Product introduction:
ADRV9008/ADRV9009 Evaluation and Prototyping Platform
ADI provides a complete set of software and hardware tools for evaluation, prototype design and reference design. The following table lists the available software and hardware tools
ADRV9009-W/PCBZ is a radio card designed to show ADRV9009 - a wide bandwidth, high performance RF integrated transceiver The radio card provides a single 2x2 transceiver platform for component evaluation and rapid prototyping of radio solutions All peripherals required for radio card operation, including a high efficiency switching power only solution and a high-performance clock solution, have been installed on the circuit board ADRV9009-W/PCBZ is a single chip TDD solution for dual channel receiver and dual channel transmitter with integrated observation receiver
ADRV9009-W/PCBZ can operate in a wide tuning range of 75MHz to 6GHz, but RF performance is modified by the front-end matching with extremely wide bandwidth This board is mainly used by the software development team to conduct system research and provide various waveforms before the completion of customized hardware The designer's goal is to view the waveform, not to care about the performance of the last 1 dB or 1% EVM
ADI official introduction page about ADRV9009 chip:
cn/products/ADRV9009.html#product -overview
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Features of chip sales:
Dual transmitter
Dual receiver
Dual input shared observation receiver
Maximum receiver bandwidth: 200 MHz
Maximum tunable transmitter synthetic bandwidth: 450 MHz
Maximum observation receiver bandwidth: 450 MHz
Fully integrated fractional N RF synthesizer
Fully integrated clock synthesizer
Multichip phase synchronization for RF LO and baseband clock
JESD204B data path interface
Tuning range: 75 MHz to 6000 MHz
Selling performance and advantages:
ADRV9009 is a highly integrated radio frequency (RF) and agile transceiver, providing dual channel transmitter and receiver, integrated frequency synthesizer and digital signal processing functions This IC has diversified high-performance and low-power combinations to meet the application requirements of 3G, 4G and 5G macro cellular time division duplex (TDD) base stations
The receiving path consists of two independent wideband, direct conversion receivers, which have a first-class dynamic range. The device also supports wideband, time sharing observation path receivers (ORx) for TDD applications The complete receiving subsystem has automatic and manual attenuation control, DC offset correction, quadrature error correction (QEC) and digital filtering functions, thus eliminating the need to provide these functions in the digital baseband It also integrates a variety of auxiliary functions, such as analog to digital converter (ADC), digital to analog converter (DAC), general input/output (GPIO) for power amplifier (PA) and RF front-end control
In addition to automatic gain control (AGC), ADRV9009 also has a flexible external gain control mode and great flexibility in dynamically setting system level gain
The received signal passes through a group of four high dynamic ranges with inherent anti aliasing characteristics for continuous time Σ-Δ ADC realizes digitalization Compared with traditional intermediate frequency (IF) receivers, the direct conversion architecture combination will not have out of band image mixing or lack of aliasing, which can reduce the requirements for RF filters
The transmitter adopts an innovative direct frequency conversion modulator, which can achieve high modulation accuracy and extremely low noise
The observation receiver path consists of a wideband, direct frequency conversion receiver with a first-class dynamic range
The fully integrated phase-locked loop (PLL) can simultaneously provide high-performance, low-power fractional N frequency division RF frequency synthesis for transmitter (Tx) and receiver (Rx) signal paths. The additional frequency synthesizer can generate the clock required by the converter, digital circuit and serial interface. The multi chip synchronous mechanism can synchronize the RF local oscillator (LO) phase and the baseband clock between multiple ADRV9009 chips. At the same time, preventive measures are taken, It also integrates voltage controlled oscillator (VCO) and loop filter element
The high-speed JESD204B interface supports a channel rate of up to 12.288 Gbps, realizing two channels per transmitter and a single channel per receiver in the broadest bandwidth mode. The interface also supports interleaving mode for lower bandwidth, thus reducing the total number of high-speed data interface channels to 1. It also supports fixed and floating data formats. The floating format makes the internal AGC invisible to the demodulator devices
The core of ADRV9009 can be directly powered by 1.3 V regulator to 1.8 V regulator and controlled through the standard four wire serial port. The comprehensive power saving mode can reduce the power consumption under normal use 12 mm for ADRV9009 × 12 mm, 196 pin chip level ball grid array package (CSP_BGA)
Sales application scenario:
3G, 4G and 5G TDD macro cellular base stations
TDD active antenna system
Large scale multiple input, multiple output (MIMO)
Phased array radar
Electronic warfare
communication
Portable test
equipment
Details of products sold:
According to the official board document and BOM, and strictly following the official production process (such as Rogers plate and three-level impedance), there is no difference between the performance and the official comparison
It can completely replace official products
The following photos show the details of the product
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