Customization: | Available |
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Type: | Development Board |
Demo Board Type: | Arm |
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The DE10-Standard Development Kit presents a robust hardware design platform built around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera's SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE10-Standard development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more.
The DE10-Standard board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.
The following hardware is provided on the board:
Cyclone V SX SoC-5CSXFC6D6F31C6N
110K LEs, 41509 ALMs
5,761 Kbits embedded memory
6 FPGA PLLs and 3 HPS PLLs
2 Hard Memory Controllers
925 MHz, Dual-Core ARM Cortex-A9 MPCore Processor
512 KB of Shared L2 Cache
64 KB of Scratch RAM
Multiport SDRAM Controller with Support for DDR2, DDR3, LPDDR1, and LPDDR2
8-Channel Direct Memory Access (DMA) Controller
Serial Configuration Device - EPCS128 on FPGA
On-Board USB Blaster II (Normal Type B USB Connector)
64MB (32Mx16) SDRAM on FPGA
1GB (2x256Mx16) DDR3 SDRAM on HPS
MicroSD Card Socket on HPS
Two USB 2.0 Host Ports (ULPI Interface with USB Type A Connector) on HPS
USB to UART (Micro USB Type B Connector) on HPS
10/100/1000 Ethernet on HPS
PS/2 Mouse/Keyboard
IR Emitter/Receiver
One 40-pin Expansion Header (Voltage Levels: 3.3V)
One HSMC Connector(Configurable I/O Standards 1.5/1.8/2.5/3.3V)
One 10-Pin ADC Input Header
One LTC Connector (One Serial Peripheral Interface (SPI) Master ,One I2C and One GPIO Interface ) on HPS
24-bit VGA DAC
128x64 Dots LCD Module with Backlight on HPS
24-bit CODEC, Line-in, Line-out, and Microphone-In Jacks
TV Decoder (NTSC/PAL/SECAM) and TV-In Connector
Sample Rate: 500 KSPS
Channel Number: 8
Resolution: 12 bits
Analog Input Range : 0 ~ 4.096 V
5 User Keys (FPGA x4, HPS x1)
10 User Switches (FPGA x10)
11 User LEDs (FPGA x10 ; HPS x 1)
2 HPS Reset Buttons (HPS_RST_n and HPS_WARM_RST_n)7-Segment Display x6
G-Sensor on HPS
12V DC Input